Hardware devices operating in a computing environment must communicate efficiently and with great speed to compete. Synchronous Dynamic Random Access Memory (SDRAM) devices, specifically Double Data Rate type Three (DDR3) SDRAM devices may be of value to a hardware manufacturer and a user. In order for a DDR3 SDRAM device to receive a communication from a controller, the controller may send a Data Lane (DQ) signal and a Data Strobe Signal (DQS) to the DDR3 SDRAM. A separate DQ and DQS may be concurrently sent on multiple paths (lanes) from controller to memory increasing transfer bandwidth. During a period of no communication, the DQS may be in a state known as “tri-state” where the DQS signal is at a unpredictable voltage level. As the SDRAM controller prepares to send a communication signal, it may first drive the DQS to a low state indicating to the SDRAM a DQ data line is forthcoming. This DQS low state is known as the preamble indicating to the SDRAM that a following DQ is on the way. One challenge for the SDRAM controller is to recognize this low state of the DQS to enable an AND gate to open for the SDRAM to receive the DQ data signal. Efficient recognition and location of the DQS preamble preceding the DQ may enable the SDRAM controller to train the AND gates for each lane to timely open allowing for proper timing of communication and capture of a valid data signal.
For DDR3, there is a DQS signal for every individual data path transiting the memory system. As the controller may send a signal, a first indicator that a signal is in transit may be when the DQS is driven from a tri-state to a low state. This DQS low state may indicate a valid DQ is en route from transmission source to reception destination and may be of at least one or more clock cycles in duration. Should the AND gate be closed the communication will not occur. However, if the gates are timed or “trained” correctly, proper communication will be received. For example, a single algorithm employed that ensures the first sample taken by the algorithm is within the driven region of the DQS may eliminate a need for trial and error sampling to determine if the first sample is within the DQS.
Previous attempts at preamble location have focused on random DQS sampling, progressive (low to high) or (left to right) DQS sampling, and delay value trial and error to sample the DQS in an attempt to find the time when the DQS was driven initially to a low state (the preamble). These attempts may begin sampling a DQS at a minimum delay value of zero and work “left to right” increasing the delay value by a step size and sampling again. This left to right method maintains no guarantee of positioning the first sample taken to be within the actively driven DQS. Additionally, a method of sampling a DQS in search of a first rising edge, may not know from where along the DQS the sample is taken rendering the method useless. Where a sample is taken from outside the actively driven DQS in the tri-stated region, random results have been observed increasing time or decreasing possibilities of preamble location and ultimately, wasting computing resources. Therefore, it is imperative the “preamble” is found first, in order to know which rising edge is the first rising edge of the DQS, and that the DQS signal is valid instead of in a tri-stated region.
U.S. Pat. No. 6,600,681 B1 to Korger et al., discloses a method for calibrating DQS qualification in a memory controller. Korger samples a DQS from a minimum delay value to a maximum delay value in an attempt to locate the preamble. However, Korger samples the DQS from left (minimum) to right (maximum) in preamble location. Such left to right sampling has proven to return arbitrary results and require a considerable number of sampling iterations before a preamble may be located.
Similarly, United States Patent Application Publication No. US 2011/0199843 A1 to Dreps et al., discloses a method and apparatus for strobe offset in bi-directional memory strobe configurations. Dreps purports to sweep a delay value from right to left, however, Dreps maintains trial and error associated with multiple iterations of a DQS sweep to eventually locate the preamble.
Therefore, it would be advantageous if a method were disclosed which provides for efficient and robust DQS preamble location and gate training while in training mode, without resorting to a resource consuming method incorporating trial and error.